In recent years, the technology of semiconductor integrated circuits has undergone a revolution aiming at higher integration and higher speeds. This technology is applied to manufacturing of semiconductor products including semiconductor memory devices, such as DRAMs, and semiconductor logic circuit devices, such as microprocessors. Therefore, the technology is positioned for extension to optimized manufacturing of semiconductor devices. Since different manufacturing technologies are embraced for the manufacture of each type of semiconductor device, there are naturally a number of problems encountered in fabricating a semiconductor memory device and a semiconductor logic circuit device on a single semiconductor chip. Under the situation, it is necessary to focus energy on how to resolve new problems for devices on a single chip which are not solved by merely extending the conventional technology. Rather focus must be on universal problems for higher integration and higher speeds. Therefore, the purpose of the present invention is to provide a high speed semiconductor integrated circuit device which comprises a semiconductor memory device and a semiconductor logic circuit device integrated in a single chip.
FIG. 12 is a block diagram of a first example of a typical conventional semiconductor integrated circuit device comprising an SDRAM core and a logic circuit which are integrated in a single chip. As shown in the figure, external input pins 101, which are connected to a logic circuit 102, forward external control signals to an SDRAM unit. The logic circuit 102 is connected to an SDRAM controller 103 which is connected to a general-purpose SDRAM core 104. An external clock input pin 105, one of the external input pins 101, supplies an external clock signal to a clock generating means 106 for feeding an internal clock signal 107 to the logic circuit 102, the SDRAM controller 103 and the general-purpose SDRAM core 104.
The clock generating means 106 is used for generating the internal clock signal 107 synchronized with the external clock signal. The clock generating means 106 may include a simple buffer, a frequency multiplier, or a frequency divider. Since the clock generating means 106 employed in the semiconductor integrated circuit device is a conventional circuit, its explanation is omitted.
The SDRAM core 104 has the same interface as a general-purpose stand-alone SDRAM. To put it in detail, signals such as a row address strobe signal 108 (referred to hereafter as a /RAS signal), a column address strobe signal 109 (referred to hereafter as a /CAS signal) and a write enable signal 110 (referred to hereafter as a WE signal) are decoded by a command decoder, and then decoded signals are input in synchronization with the rising edge of the internal clock signal 107 as a command for controlling the operation of the SDRAM core 104.
The SDRAM core 104 receives the /RAS signal 108, the /CAS signal 109, the /WE signal 110, an address 111 and a data input 112 from the SDRAM controller 103. In response to the /RAS signal 108, the /CAS signal 109, and the address 111, the SDRAM core 104 generates a data output 113 supplied to the SDRAM controller 103.
Examples of commands output by the command decoder as a result of decoding the /RAS signal 108, the /CAS signal 109 and the /WE signal 110 are listed in the following table.
______________________________________ /RAS /CAS /WE ______________________________________ Bank activate L H H Precharge L H L Write H L L Read H L H Refresh L L H ______________________________________
In the case of a general-purpose stand-alone SDRAM unit, the number of external pins is limited. Thus, a technique for decoding such external control signals is adopted. In this way, detailed commands, such as Bank Activate (ACT) 114, Precharge (PRC) 115, Write 116, Read 117, and Refresh (REF) 118 can be given using a small number of such external signals.
Internal control signals, that is, the Bank Activate (ACT) command 114, the Precharge (PRC) command 115, the Write command 116, the Read command 117, and the Refresh (REF) command 118, output by the command decoder are each supplied to an input synchronizing latch. The internal synchronizing latch receives an internal control signal in synchronization with the internal clock signal 107.
In a timing generation circuit, an internal operation signal required for the operation of the SDRAM core is generated from the signal latched in the input synchronizing latch, supplying the internal operation signal to a memory array. Read-out data output from the memory array in response to the internal operation signal is supplied to an output control circuit.
Data is supplied to the SDRAM core 104 in a write operation and is to be output later in a read operation as a data output 113 from the output control circuit in synchronization with the internal clock signal 107. The data output 113 is supplied to the SDRAM controller 103.
FIGS. 13(A)-13(K) comprise a timing chart showing the operation of the typical conventional semiconductor integrated circuit device shown in FIG. 12. While receiving inputs from the logic circuit 102, the SDRAM controller 103 generates the /RAS signal 108, the /CAS signal 109, the /WE signal 110, an address 111, and a data input 112 synchronized with the internal clock signal 107. When these synchronized signals are produced, a delay time t(control) is generated in the propagation of each of the signals through the SDRAM controller 103. Then, when a synchronized signal is decoded by the command decoder inside the SDRAM core 104, a delay time t(dec) is further generated. As a result, there is a total delay time (t(control)+t(dec)) between the generation of the signals synchronized with the rising edge of the internal clock signal 107 and the generation of the Bank Activate (ACT) command 114, the Precharge (CRC) command 115, the Write command 116, the Read command 117, and the Refresh (REF) command 118.
Therefore, in order to enable the SDRAM core 104 to recognize the commands correctly, the period t(clock) of the internal clock signal 107 must satisfy the following relation: EQU t(clock)&gt;t(control)+t(dec)+t(set-up) (1)
(where t(set-up) denotes a set-up time.)
In recent years, however, the operating frequency of SDRAMs has been increased to around 160 MHz, which corresponds to a period t(clock) of about 6 ns. In order to preserve a sufficient set-up time t (set-up) and to implement a stable operation, it is therefore necessary to minimize the total delay time (t(control)+t(dec)).
FIG. 14 is a block diagram showing a second example of a typical conventional semiconductor integrated circuit device comprising an SDRAM core and a logic circuit which are integrated in a single chip. In a semiconductor integrated circuit device comprising a memory core of mainly an SDRAM and a logic circuit device integrated in a single chip, a circuit configuration is generally adopted which allows the memory core to be tested through external pins as a stand-alone unit.
The semiconductor integrated circuit device shown in FIG. 14 is different from that shown in FIG. 12 in that the former external test pins normally including a normal/test switch pin 119, a test RAS pin 120, a test CAS pin 121, a test WE pin 122, test address pins 123, test data input pins 124, and test data output pins 125.
A normal/test switch signal 126, a test RAS signal 127, a test CAS signal 128, a test WE signal 129, a test address signal 130, a test data input signal 131 and a test data output signal 132 are supplied to the normal/test switch pin 119, the test /RAS pin 120, the test /CAS pin 121, the test /WE pin 122, the test address pins 123, the test data input pins 124, and the test data output pins 113 respectively.
The /RAS signal 108, the /CAS signal 109, the /WE signal 110, an address 111, and a data input 112 are supplied to the SDRAM core 104 by way of a two-to-one selector to which the normal/test switch signal 126 is fed as a select signal. In detail, the two-to-one selector selects either a normal RAS signal 132, a normal CAS signal 133, a normal WE signal 134, a normal address signal 135, and a normal data input 136 supplied by the SDRAM controller 103 or the test RAS signal 127, the test CAS signal 128, the test WE signal 129, the test address signal 130, and the test data input signal 131 received from the test RAS pin 120, the test CAS pin 121, the test WE pin 122, the test address pins 123, and the test data input pins 124, respectively, in accordance with the normal/test switch signal 126 supplied from the normal/test switch pin 119. In a normal operation, the signals supplied by the SDRAM controller 103 are selected. When testing the memory core as a stand-alone unit, on the other hand, the test signals supplied from the external test pins are selected.
FIGS. 15(A)-15(Q) comprise a timing chart showing the operation of the second typical conventional semiconductor integrated circuit device shown in FIG. 14 in a normal operation. The operation of this conventional semiconductor integrated circuit device is different from the operation shown in FIGS. 13(A)-13(K) in that, in a normal operation, a delay time t(sel) caused by the two-to-one selector is further generated. Therefore, in order to enable the SDRAM core 104 to recognize the commands correctly, the period t(clock) of the internal clock signal 107 must satisfy the following relation: EQU t(clock)&gt;t(control)+t(sel)+t(dec)+t(set-up) (2)
It is obvious from the above relation that the timing condition for the second typical conventional semiconductor integrated circuit device is more severe than for the circuit shown in FIG. 12. Thus, the conventional SDRAMs described above have some problems, as follows.
(a) In the first place, the conventional SDRAMs can not keep up with operations at higher operating frequencies at which SDRAMs produced in recent years operate. The delay time of the decoder circuit described above is about 1 ns. At an operating frequency of about 160 MHz, the clock period is about 6 ns. As a result, the delay time of the decoder circuit is a hindrance to an effort to increase the operating frequency of the SDRAM.
(b) In the second place, an input buffer for signals generated in the logic circuit as well as an SDRAM test circuit and a selector which are not naturally used in a normal operation but required for testing are provided, causing delay in the propagation of the RAS, CAS, and WE signals and others and resulting in differences in delay times among these signals. The delay time and the differences in delay times are also a hindrance to speed improvement and stable operation of the SDRAM.